Layer Information
| layer_index | layer_name | layer_type | layer_shape | layer_duration (us) | layer_allocated_bytes | layer_peak_allocated_bytes | layer_allocator_bytes_in_use | layer_allocator_name | layer_host_temp_mem_bytes | layer_device_temp_mem_bytes | layer_host_persistent_mem_bytes | layer_device_persistent_mem_bytes |
|---|
layer_index | layer_name | layer_type | layer_shape | layer_duration (us) | layer_allocated_bytes | layer_peak_allocated_bytes | layer_allocator_bytes_in_use | layer_allocator_name | layer_host_temp_mem_bytes | layer_device_temp_mem_bytes | layer_host_persistent_mem_bytes | layer_device_persistent_mem_bytes |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | InceptionV4/InceptionV4/Conv2d_1a_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 149 149 32]] | 2262 | 2841728 | 2841728 | 0 | cpu | 0 | 0 | 0 | 0 |
| 3 | InceptionV4/InceptionV4/Conv2d_1a_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 149 149 32]] | 351.667 | 2841728 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 4 | InceptionV4/InceptionV4/Conv2d_1a_3x3/Relu | Relu | [[1 149 149 32]] | 130.667 | 2841728 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 5 | InceptionV4/InceptionV4/Conv2d_2a_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 147 147 32]] | 3898.667 | 2765952 | 2765952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 6 | InceptionV4/InceptionV4/Conv2d_2a_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 147 147 32]] | 343.667 | 2765952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 7 | InceptionV4/InceptionV4/Conv2d_2a_3x3/Relu | Relu | [[1 147 147 32]] | 136.667 | 2765952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 8 | InceptionV4/InceptionV4/Conv2d_2b_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 147 147 64]] | 6003.667 | 5531904 | 5531904 | 0 | cpu | 0 | 0 | 0 | 0 |
| 9 | InceptionV4/InceptionV4/Conv2d_2b_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 147 147 64]] | 515.667 | 5531904 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 10 | InceptionV4/InceptionV4/Conv2d_2b_3x3/Relu | Relu | [[1 147 147 64]] | 162 | 5531904 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 11 | InceptionV4/InceptionV4/Mixed_3a/Branch_0/MaxPool_0a_3x3/MaxPool | MaxPool | [[1 73 73 64]] | 1745.333 | 1364224 | 1364224 | 0 | cpu | 0 | 0 | 0 | 0 |
| 12 | InceptionV4/InceptionV4/Mixed_3a/Branch_1/Conv2d_0a_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 73 73 96]] | 4868 | 2046336 | 2046336 | 0 | cpu | 0 | 0 | 0 | 0 |
| 13 | InceptionV4/InceptionV4/Mixed_3a/Branch_1/Conv2d_0a_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 73 73 96]] | 273 | 2046336 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 14 | InceptionV4/InceptionV4/Mixed_3a/Branch_1/Conv2d_0a_3x3/Relu | Relu | [[1 73 73 96]] | 123 | 2046336 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 15 | InceptionV4/InceptionV4/Mixed_3a/concat | ConcatV2 | [[1 73 73 160]] | 268 | 3410560 | 3410560 | 0 | cpu | 0 | 0 | 0 | 0 |
| 16 | InceptionV4/InceptionV4/Mixed_4a/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 73 73 64]] | 1706 | 1364224 | 1364224 | 0 | cpu | 0 | 0 | 0 | 0 |
| 17 | InceptionV4/InceptionV4/Mixed_4a/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 73 73 64]] | 1585.667 | 1364224 | 1364224 | 0 | cpu | 0 | 0 | 0 | 0 |
| 18 | InceptionV4/InceptionV4/Mixed_4a/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 73 73 64]] | 230 | 1364224 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 19 | InceptionV4/InceptionV4/Mixed_4a/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 73 73 64]] | 349 | 1364224 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 20 | InceptionV4/InceptionV4/Mixed_4a/Branch_1/Conv2d_0a_1x1/Relu | Relu | [[1 73 73 64]] | 97.667 | 1364224 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 21 | InceptionV4/InceptionV4/Mixed_4a/Branch_0/Conv2d_0a_1x1/Relu | Relu | [[1 73 73 64]] | 118.333 | 1364224 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 22 | InceptionV4/InceptionV4/Mixed_4a/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 73 73 64]] | 4689.333 | 1364224 | 1364224 | 0 | cpu | 0 | 0 | 0 | 0 |
| 23 | InceptionV4/InceptionV4/Mixed_4a/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 73 73 64]] | 294.333 | 1364224 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 24 | InceptionV4/InceptionV4/Mixed_4a/Branch_1/Conv2d_0b_1x7/Relu | Relu | [[1 73 73 64]] | 467.333 | 1364224 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 25 | InceptionV4/InceptionV4/Mixed_4a/Branch_0/Conv2d_1a_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 71 71 96]] | 6435.667 | 1935744 | 1935744 | 0 | cpu | 0 | 0 | 0 | 0 |
| 26 | InceptionV4/InceptionV4/Mixed_4a/Branch_0/Conv2d_1a_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 71 71 96]] | 688.333 | 1935744 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 27 | InceptionV4/InceptionV4/Mixed_4a/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 73 73 64]] | 2843.333 | 1364224 | 1364224 | 0 | cpu | 0 | 0 | 0 | 0 |
| 28 | InceptionV4/InceptionV4/Mixed_4a/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 73 73 64]] | 229.333 | 1364224 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 29 | InceptionV4/InceptionV4/Mixed_4a/Branch_1/Conv2d_0c_7x1/Relu | Relu | [[1 73 73 64]] | 89 | 1364224 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 30 | InceptionV4/InceptionV4/Mixed_4a/Branch_1/Conv2d_1a_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 71 71 96]] | 3978.667 | 1935744 | 1935744 | 0 | cpu | 0 | 0 | 0 | 0 |
| 31 | InceptionV4/InceptionV4/Mixed_4a/Branch_1/Conv2d_1a_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 71 71 96]] | 234.333 | 1935744 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 32 | InceptionV4/InceptionV4/Mixed_4a/concat | ConcatV2 | [[1 71 71 192]] | 255 | 3871488 | 3871488 | 0 | cpu | 0 | 0 | 0 | 0 |
| 33 | InceptionV4/InceptionV4/Mixed_4a/Branch_0/Conv2d_1a_3x3/Relu | Relu | [[1 71 71 192]] | 152 | 3871488 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 34 | InceptionV4/InceptionV4/Mixed_5a/Branch_1/MaxPool_1a_3x3/MaxPool | MaxPool | [[1 35 35 192]] | 828 | 940800 | 940800 | 0 | cpu | 0 | 0 | 0 | 0 |
| 35 | InceptionV4/InceptionV4/Mixed_5a/Branch_0/Conv2d_1a_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 192]] | 5657.333 | 940800 | 940800 | 0 | cpu | 0 | 0 | 0 | 0 |
| 36 | InceptionV4/InceptionV4/Mixed_5a/Branch_0/Conv2d_1a_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 192]] | 190 | 940800 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 37 | InceptionV4/InceptionV4/Mixed_5a/Branch_0/Conv2d_1a_3x3/Relu | Relu | [[1 35 35 192]] | 102.333 | 940800 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 38 | InceptionV4/InceptionV4/Mixed_5a/concat | ConcatV2 | [[1 35 35 384]] | 179 | 1881600 | 1881600 | 0 | cpu | 0 | 0 | 0 | 0 |
| 39 | InceptionV4/InceptionV4/Mixed_5b/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 64]] | 1842.667 | 313600 | 313600 | 0 | cpu | 0 | 0 | 0 | 0 |
| 40 | InceptionV4/InceptionV4/Mixed_5b/Branch_3/AvgPool_0a_3x3/AvgPool | AvgPool | [[1 35 35 384]] | 2008.333 | 1881600 | 1881600 | 0 | cpu | 0 | 0 | 0 | 0 |
| 41 | InceptionV4/InceptionV4/Mixed_5b/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 64]] | 161 | 313600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 42 | InceptionV4/InceptionV4/Mixed_5b/Branch_1/Conv2d_0a_1x1/Relu | Relu | [[1 35 35 64]] | 31 | 313600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 43 | InceptionV4/InceptionV4/Mixed_5b/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 2005 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 44 | InceptionV4/InceptionV4/Mixed_5b/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 64]] | 1833 | 313600 | 313600 | 0 | cpu | 0 | 0 | 0 | 0 |
| 45 | InceptionV4/InceptionV4/Mixed_5b/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 355.333 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 46 | InceptionV4/InceptionV4/Mixed_5b/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 64]] | 179.667 | 313600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 47 | InceptionV4/InceptionV4/Mixed_5b/Branch_2/Conv2d_0a_1x1/Relu | Relu | [[1 35 35 64]] | 36.333 | 313600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 48 | InceptionV4/InceptionV4/Mixed_5b/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 2378.333 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 49 | InceptionV4/InceptionV4/Mixed_5b/Branch_1/Conv2d_0b_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 2419.333 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 50 | InceptionV4/InceptionV4/Mixed_5b/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 250.333 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 51 | InceptionV4/InceptionV4/Mixed_5b/Branch_1/Conv2d_0b_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 289.667 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 52 | InceptionV4/InceptionV4/Mixed_5b/Branch_2/Conv2d_0b_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 2624.667 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 53 | InceptionV4/InceptionV4/Mixed_5b/Branch_2/Conv2d_0b_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 139.333 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 54 | InceptionV4/InceptionV4/Mixed_5b/Branch_2/Conv2d_0b_3x3/Relu | Relu | [[1 35 35 96]] | 84 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 55 | InceptionV4/InceptionV4/Mixed_5b/Branch_2/Conv2d_0c_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 1565 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 56 | InceptionV4/InceptionV4/Mixed_5b/Branch_2/Conv2d_0c_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 137.667 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 57 | InceptionV4/InceptionV4/Mixed_5b/concat | ConcatV2 | [[1 35 35 384]] | 176.667 | 1881600 | 1881600 | 0 | cpu | 0 | 0 | 0 | 0 |
| 58 | InceptionV4/InceptionV4/Mixed_5b/Branch_0/Conv2d_0a_1x1/Relu | Relu | [[1 35 35 384]] | 126.333 | 1881600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 59 | InceptionV4/InceptionV4/Mixed_5c/Branch_3/AvgPool_0a_3x3/AvgPool | AvgPool | [[1 35 35 384]] | 1789.333 | 1881600 | 1881600 | 0 | cpu | 0 | 0 | 0 | 0 |
| 60 | InceptionV4/InceptionV4/Mixed_5c/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 64]] | 1911.333 | 313600 | 313600 | 0 | cpu | 0 | 0 | 0 | 0 |
| 61 | InceptionV4/InceptionV4/Mixed_5c/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 64]] | 281.333 | 313600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 62 | InceptionV4/InceptionV4/Mixed_5c/Branch_1/Conv2d_0a_1x1/Relu | Relu | [[1 35 35 64]] | 32 | 313600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 63 | InceptionV4/InceptionV4/Mixed_5c/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 2075.333 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 64 | InceptionV4/InceptionV4/Mixed_5c/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 287.667 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 65 | InceptionV4/InceptionV4/Mixed_5c/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 64]] | 2409 | 313600 | 313600 | 0 | cpu | 0 | 0 | 0 | 0 |
| 66 | InceptionV4/InceptionV4/Mixed_5c/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 64]] | 218 | 313600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 67 | InceptionV4/InceptionV4/Mixed_5c/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 2096.667 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 68 | InceptionV4/InceptionV4/Mixed_5c/Branch_2/Conv2d_0a_1x1/Relu | Relu | [[1 35 35 64]] | 34 | 313600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 69 | InceptionV4/InceptionV4/Mixed_5c/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 334 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 70 | InceptionV4/InceptionV4/Mixed_5c/Branch_1/Conv2d_0b_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 2608.333 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 71 | InceptionV4/InceptionV4/Mixed_5c/Branch_1/Conv2d_0b_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 166 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 72 | InceptionV4/InceptionV4/Mixed_5c/Branch_2/Conv2d_0b_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 2464 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 73 | InceptionV4/InceptionV4/Mixed_5c/Branch_2/Conv2d_0b_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 122 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 74 | InceptionV4/InceptionV4/Mixed_5c/Branch_2/Conv2d_0b_3x3/Relu | Relu | [[1 35 35 96]] | 76.667 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 75 | InceptionV4/InceptionV4/Mixed_5c/Branch_2/Conv2d_0c_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 1551.667 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 76 | InceptionV4/InceptionV4/Mixed_5c/Branch_2/Conv2d_0c_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 134.667 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 77 | InceptionV4/InceptionV4/Mixed_5c/concat | ConcatV2 | [[1 35 35 384]] | 180 | 1881600 | 1881600 | 0 | cpu | 0 | 0 | 0 | 0 |
| 78 | InceptionV4/InceptionV4/Mixed_5c/Branch_0/Conv2d_0a_1x1/Relu | Relu | [[1 35 35 384]] | 122.333 | 1881600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 79 | InceptionV4/InceptionV4/Mixed_5d/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 64]] | 1678.667 | 313600 | 313600 | 0 | cpu | 0 | 0 | 0 | 0 |
| 80 | InceptionV4/InceptionV4/Mixed_5d/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 64]] | 206.667 | 313600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 81 | InceptionV4/InceptionV4/Mixed_5d/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 1875 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 82 | InceptionV4/InceptionV4/Mixed_5d/Branch_1/Conv2d_0a_1x1/Relu | Relu | [[1 35 35 64]] | 32.667 | 313600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 83 | InceptionV4/InceptionV4/Mixed_5d/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 456.333 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 84 | InceptionV4/InceptionV4/Mixed_5d/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 64]] | 1802.333 | 313600 | 313600 | 0 | cpu | 0 | 0 | 0 | 0 |
| 85 | InceptionV4/InceptionV4/Mixed_5d/Branch_3/AvgPool_0a_3x3/AvgPool | AvgPool | [[1 35 35 384]] | 1962 | 1881600 | 1881600 | 0 | cpu | 0 | 0 | 0 | 0 |
| 86 | InceptionV4/InceptionV4/Mixed_5d/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 64]] | 188.333 | 313600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 87 | InceptionV4/InceptionV4/Mixed_5d/Branch_2/Conv2d_0a_1x1/Relu | Relu | [[1 35 35 64]] | 35.667 | 313600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 88 | InceptionV4/InceptionV4/Mixed_5d/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 1896.333 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 89 | InceptionV4/InceptionV4/Mixed_5d/Branch_1/Conv2d_0b_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 2564.667 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 90 | InceptionV4/InceptionV4/Mixed_5d/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 387 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 91 | InceptionV4/InceptionV4/Mixed_5d/Branch_2/Conv2d_0b_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 2679 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 92 | InceptionV4/InceptionV4/Mixed_5d/Branch_1/Conv2d_0b_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 161 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 93 | InceptionV4/InceptionV4/Mixed_5d/Branch_2/Conv2d_0b_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 154.667 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 94 | InceptionV4/InceptionV4/Mixed_5d/Branch_2/Conv2d_0b_3x3/Relu | Relu | [[1 35 35 96]] | 82.667 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 95 | InceptionV4/InceptionV4/Mixed_5d/Branch_2/Conv2d_0c_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 1557.667 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 96 | InceptionV4/InceptionV4/Mixed_5d/Branch_2/Conv2d_0c_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 148 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 97 | InceptionV4/InceptionV4/Mixed_5d/concat | ConcatV2 | [[1 35 35 384]] | 173.667 | 1881600 | 1881600 | 0 | cpu | 0 | 0 | 0 | 0 |
| 98 | InceptionV4/InceptionV4/Mixed_5d/Branch_0/Conv2d_0a_1x1/Relu | Relu | [[1 35 35 384]] | 120.333 | 1881600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 99 | InceptionV4/InceptionV4/Mixed_5e/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 64]] | 1685.667 | 313600 | 313600 | 0 | cpu | 0 | 0 | 0 | 0 |
| 100 | InceptionV4/InceptionV4/Mixed_5e/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 64]] | 1824.333 | 313600 | 313600 | 0 | cpu | 0 | 0 | 0 | 0 |
| 101 | InceptionV4/InceptionV4/Mixed_5e/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 1846.667 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 102 | InceptionV4/InceptionV4/Mixed_5e/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 64]] | 164.667 | 313600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 103 | InceptionV4/InceptionV4/Mixed_5e/Branch_3/AvgPool_0a_3x3/AvgPool | AvgPool | [[1 35 35 384]] | 1923.333 | 1881600 | 1881600 | 0 | cpu | 0 | 0 | 0 | 0 |
| 104 | InceptionV4/InceptionV4/Mixed_5e/Branch_2/Conv2d_0a_1x1/Relu | Relu | [[1 35 35 64]] | 32.667 | 313600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 105 | InceptionV4/InceptionV4/Mixed_5e/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 64]] | 133.667 | 313600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 106 | InceptionV4/InceptionV4/Mixed_5e/Branch_1/Conv2d_0a_1x1/Relu | Relu | [[1 35 35 64]] | 37.333 | 313600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 107 | InceptionV4/InceptionV4/Mixed_5e/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 152.333 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 108 | InceptionV4/InceptionV4/Mixed_5e/Branch_1/Conv2d_0b_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 2559.667 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 109 | InceptionV4/InceptionV4/Mixed_5e/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 2057.667 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 110 | InceptionV4/InceptionV4/Mixed_5e/Branch_1/Conv2d_0b_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 151 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 111 | InceptionV4/InceptionV4/Mixed_5e/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 315 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 112 | InceptionV4/InceptionV4/Mixed_5e/Branch_2/Conv2d_0b_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 2668.333 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 113 | InceptionV4/InceptionV4/Mixed_5e/Branch_2/Conv2d_0b_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 169 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 114 | InceptionV4/InceptionV4/Mixed_5e/Branch_2/Conv2d_0b_3x3/Relu | Relu | [[1 35 35 96]] | 91.667 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 115 | InceptionV4/InceptionV4/Mixed_5e/Branch_2/Conv2d_0c_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 96]] | 1559.333 | 470400 | 470400 | 0 | cpu | 0 | 0 | 0 | 0 |
| 116 | InceptionV4/InceptionV4/Mixed_5e/Branch_2/Conv2d_0c_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 96]] | 144 | 470400 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 117 | InceptionV4/InceptionV4/Mixed_5e/concat | ConcatV2 | [[1 35 35 384]] | 175 | 1881600 | 1881600 | 0 | cpu | 0 | 0 | 0 | 0 |
| 118 | InceptionV4/InceptionV4/Mixed_5e/Branch_0/Conv2d_0a_1x1/Relu | Relu | [[1 35 35 384]] | 124.667 | 1881600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 119 | InceptionV4/InceptionV4/Mixed_6a/Branch_2/MaxPool_1a_3x3/MaxPool | MaxPool | [[1 17 17 384]] | 372.333 | 443904 | 443904 | 0 | cpu | 0 | 0 | 0 | 0 |
| 120 | InceptionV4/InceptionV4/Mixed_6a/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 192]] | 2423.333 | 940800 | 940800 | 0 | cpu | 0 | 0 | 0 | 0 |
| 121 | InceptionV4/InceptionV4/Mixed_6a/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 192]] | 527 | 940800 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 122 | InceptionV4/InceptionV4/Mixed_6a/Branch_1/Conv2d_0a_1x1/Relu | Relu | [[1 35 35 192]] | 146 | 940800 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 123 | InceptionV4/InceptionV4/Mixed_6a/Branch_1/Conv2d_0b_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 35 35 224]] | 9916.667 | 1097600 | 1097600 | 0 | cpu | 0 | 0 | 0 | 0 |
| 124 | InceptionV4/InceptionV4/Mixed_6a/Branch_0/Conv2d_1a_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 384]] | 11491 | 443904 | 443904 | 0 | cpu | 0 | 0 | 0 | 0 |
| 125 | InceptionV4/InceptionV4/Mixed_6a/Branch_1/Conv2d_0b_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 35 35 224]] | 197 | 1097600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 126 | InceptionV4/InceptionV4/Mixed_6a/Branch_1/Conv2d_0b_3x3/Relu | Relu | [[1 35 35 224]] | 93.667 | 1097600 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 127 | InceptionV4/InceptionV4/Mixed_6a/Branch_0/Conv2d_1a_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 384]] | 323.667 | 443904 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 128 | InceptionV4/InceptionV4/Mixed_6a/Branch_0/Conv2d_1a_3x3/Relu | Relu | [[1 17 17 384]] | 82.333 | 443904 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 129 | InceptionV4/InceptionV4/Mixed_6a/Branch_1/Conv2d_1a_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 256]] | 2248 | 295936 | 295936 | 0 | cpu | 0 | 0 | 0 | 0 |
| 130 | InceptionV4/InceptionV4/Mixed_6a/Branch_1/Conv2d_1a_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 256]] | 112.333 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 131 | InceptionV4/InceptionV4/Mixed_6a/Branch_1/Conv2d_1a_3x3/Relu | Relu | [[1 17 17 256]] | 36.667 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 132 | InceptionV4/InceptionV4/Mixed_6a/concat | ConcatV2 | [[1 17 17 1024]] | 167.333 | 1183744 | 1183744 | 0 | cpu | 0 | 0 | 0 | 0 |
| 133 | InceptionV4/InceptionV4/Mixed_6b/Branch_3/AvgPool_0a_3x3/AvgPool | AvgPool | [[1 17 17 1024]] | 1167 | 1183744 | 1183744 | 0 | cpu | 0 | 0 | 0 | 0 |
| 134 | InceptionV4/InceptionV4/Mixed_6b/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 3279.667 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 135 | InceptionV4/InceptionV4/Mixed_6b/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 3235 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 136 | InceptionV4/InceptionV4/Mixed_6b/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 152.667 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 137 | InceptionV4/InceptionV4/Mixed_6b/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 384]] | 4424.667 | 443904 | 443904 | 0 | cpu | 0 | 0 | 0 | 0 |
| 138 | InceptionV4/InceptionV4/Mixed_6b/Branch_2/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 192]] | 26.667 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 139 | InceptionV4/InceptionV4/Mixed_6b/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 143.667 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 140 | InceptionV4/InceptionV4/Mixed_6b/Branch_1/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 192]] | 27 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 141 | InceptionV4/InceptionV4/Mixed_6b/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 384]] | 198.667 | 443904 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 142 | InceptionV4/InceptionV4/Mixed_6b/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 128]] | 2566.333 | 147968 | 147968 | 0 | cpu | 0 | 0 | 0 | 0 |
| 143 | InceptionV4/InceptionV4/Mixed_6b/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 128]] | 131.333 | 147968 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 144 | InceptionV4/InceptionV4/Mixed_6b/Branch_2/Conv2d_0b_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 2422.667 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 145 | InceptionV4/InceptionV4/Mixed_6b/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 2585.667 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 146 | InceptionV4/InceptionV4/Mixed_6b/Branch_2/Conv2d_0b_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 153.667 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 147 | InceptionV4/InceptionV4/Mixed_6b/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 129 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 148 | InceptionV4/InceptionV4/Mixed_6b/Branch_2/Conv2d_0b_7x1/Relu | Relu | [[1 17 17 192]] | 25 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 149 | InceptionV4/InceptionV4/Mixed_6b/Branch_1/Conv2d_0b_1x7/Relu | Relu | [[1 17 17 224]] | 30.333 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 150 | InceptionV4/InceptionV4/Mixed_6b/Branch_2/Conv2d_0c_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 2305.667 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 151 | InceptionV4/InceptionV4/Mixed_6b/Branch_2/Conv2d_0c_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 132 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 152 | InceptionV4/InceptionV4/Mixed_6b/Branch_2/Conv2d_0c_1x7/Relu | Relu | [[1 17 17 224]] | 29 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 153 | InceptionV4/InceptionV4/Mixed_6b/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 256]] | 3111 | 295936 | 295936 | 0 | cpu | 0 | 0 | 0 | 0 |
| 154 | InceptionV4/InceptionV4/Mixed_6b/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 256]] | 140 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 155 | InceptionV4/InceptionV4/Mixed_6b/Branch_2/Conv2d_0d_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 1833 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 156 | InceptionV4/InceptionV4/Mixed_6b/Branch_2/Conv2d_0d_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 103.333 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 157 | InceptionV4/InceptionV4/Mixed_6b/Branch_2/Conv2d_0d_7x1/Relu | Relu | [[1 17 17 224]] | 30.667 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 158 | InceptionV4/InceptionV4/Mixed_6b/Branch_2/Conv2d_0e_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 256]] | 1757.333 | 295936 | 295936 | 0 | cpu | 0 | 0 | 0 | 0 |
| 159 | InceptionV4/InceptionV4/Mixed_6b/Branch_2/Conv2d_0e_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 256]] | 112.667 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 160 | InceptionV4/InceptionV4/Mixed_6b/concat | ConcatV2 | [[1 17 17 1024]] | 161.333 | 1183744 | 1183744 | 0 | cpu | 0 | 0 | 0 | 0 |
| 161 | InceptionV4/InceptionV4/Mixed_6b/Branch_0/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 1024]] | 116.667 | 1183744 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 162 | InceptionV4/InceptionV4/Mixed_6c/Branch_3/AvgPool_0a_3x3/AvgPool | AvgPool | [[1 17 17 1024]] | 1141.667 | 1183744 | 1183744 | 0 | cpu | 0 | 0 | 0 | 0 |
| 163 | InceptionV4/InceptionV4/Mixed_6c/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 3973.333 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 164 | InceptionV4/InceptionV4/Mixed_6c/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 3502.333 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 165 | InceptionV4/InceptionV4/Mixed_6c/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 237.333 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 166 | InceptionV4/InceptionV4/Mixed_6c/Branch_2/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 192]] | 27 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 167 | InceptionV4/InceptionV4/Mixed_6c/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 170.333 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 168 | InceptionV4/InceptionV4/Mixed_6c/Branch_1/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 192]] | 26.667 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 169 | InceptionV4/InceptionV4/Mixed_6c/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 128]] | 2870.333 | 147968 | 147968 | 0 | cpu | 0 | 0 | 0 | 0 |
| 170 | InceptionV4/InceptionV4/Mixed_6c/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 128]] | 305.333 | 147968 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 171 | InceptionV4/InceptionV4/Mixed_6c/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 384]] | 4948 | 443904 | 443904 | 0 | cpu | 0 | 0 | 0 | 0 |
| 172 | InceptionV4/InceptionV4/Mixed_6c/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 384]] | 221.333 | 443904 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 173 | InceptionV4/InceptionV4/Mixed_6c/Branch_2/Conv2d_0b_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 2365.333 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 174 | InceptionV4/InceptionV4/Mixed_6c/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 2871.667 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 175 | InceptionV4/InceptionV4/Mixed_6c/Branch_2/Conv2d_0b_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 180.667 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 176 | InceptionV4/InceptionV4/Mixed_6c/Branch_2/Conv2d_0b_7x1/Relu | Relu | [[1 17 17 192]] | 26.333 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 177 | InceptionV4/InceptionV4/Mixed_6c/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 150.667 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 178 | InceptionV4/InceptionV4/Mixed_6c/Branch_1/Conv2d_0b_1x7/Relu | Relu | [[1 17 17 224]] | 31 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 179 | InceptionV4/InceptionV4/Mixed_6c/Branch_2/Conv2d_0c_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 2211 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 180 | InceptionV4/InceptionV4/Mixed_6c/Branch_2/Conv2d_0c_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 142.333 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 181 | InceptionV4/InceptionV4/Mixed_6c/Branch_2/Conv2d_0c_1x7/Relu | Relu | [[1 17 17 224]] | 29.667 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 182 | InceptionV4/InceptionV4/Mixed_6c/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 256]] | 3033 | 295936 | 295936 | 0 | cpu | 0 | 0 | 0 | 0 |
| 183 | InceptionV4/InceptionV4/Mixed_6c/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 256]] | 129.333 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 184 | InceptionV4/InceptionV4/Mixed_6c/Branch_2/Conv2d_0d_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 1800 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 185 | InceptionV4/InceptionV4/Mixed_6c/Branch_2/Conv2d_0d_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 106 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 186 | InceptionV4/InceptionV4/Mixed_6c/Branch_2/Conv2d_0d_7x1/Relu | Relu | [[1 17 17 224]] | 29.667 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 187 | InceptionV4/InceptionV4/Mixed_6c/Branch_2/Conv2d_0e_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 256]] | 1719 | 295936 | 295936 | 0 | cpu | 0 | 0 | 0 | 0 |
| 188 | InceptionV4/InceptionV4/Mixed_6c/Branch_2/Conv2d_0e_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 256]] | 112.667 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 189 | InceptionV4/InceptionV4/Mixed_6c/concat | ConcatV2 | [[1 17 17 1024]] | 159 | 1183744 | 1183744 | 0 | cpu | 0 | 0 | 0 | 0 |
| 190 | InceptionV4/InceptionV4/Mixed_6c/Branch_0/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 1024]] | 114 | 1183744 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 191 | InceptionV4/InceptionV4/Mixed_6d/Branch_3/AvgPool_0a_3x3/AvgPool | AvgPool | [[1 17 17 1024]] | 1174.667 | 1183744 | 1183744 | 0 | cpu | 0 | 0 | 0 | 0 |
| 192 | InceptionV4/InceptionV4/Mixed_6d/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 3506.667 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 193 | InceptionV4/InceptionV4/Mixed_6d/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 259.333 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 194 | InceptionV4/InceptionV4/Mixed_6d/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 3735 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 195 | InceptionV4/InceptionV4/Mixed_6d/Branch_1/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 192]] | 26 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 196 | InceptionV4/InceptionV4/Mixed_6d/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 384]] | 4603.667 | 443904 | 443904 | 0 | cpu | 0 | 0 | 0 | 0 |
| 197 | InceptionV4/InceptionV4/Mixed_6d/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 384]] | 321 | 443904 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 198 | InceptionV4/InceptionV4/Mixed_6d/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 128]] | 2646.667 | 147968 | 147968 | 0 | cpu | 0 | 0 | 0 | 0 |
| 199 | InceptionV4/InceptionV4/Mixed_6d/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 388 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 200 | InceptionV4/InceptionV4/Mixed_6d/Branch_2/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 192]] | 26 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 201 | InceptionV4/InceptionV4/Mixed_6d/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 128]] | 138.333 | 147968 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 202 | InceptionV4/InceptionV4/Mixed_6d/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 2696 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 203 | InceptionV4/InceptionV4/Mixed_6d/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 95.333 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 204 | InceptionV4/InceptionV4/Mixed_6d/Branch_1/Conv2d_0b_1x7/Relu | Relu | [[1 17 17 224]] | 28.667 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 205 | InceptionV4/InceptionV4/Mixed_6d/Branch_2/Conv2d_0b_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 2225.667 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 206 | InceptionV4/InceptionV4/Mixed_6d/Branch_2/Conv2d_0b_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 140.667 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 207 | InceptionV4/InceptionV4/Mixed_6d/Branch_2/Conv2d_0b_7x1/Relu | Relu | [[1 17 17 192]] | 26.667 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 208 | InceptionV4/InceptionV4/Mixed_6d/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 256]] | 3013.333 | 295936 | 295936 | 0 | cpu | 0 | 0 | 0 | 0 |
| 209 | InceptionV4/InceptionV4/Mixed_6d/Branch_2/Conv2d_0c_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 2498.667 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 210 | InceptionV4/InceptionV4/Mixed_6d/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 256]] | 192.333 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 211 | InceptionV4/InceptionV4/Mixed_6d/Branch_2/Conv2d_0c_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 114.667 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 212 | InceptionV4/InceptionV4/Mixed_6d/Branch_2/Conv2d_0c_1x7/Relu | Relu | [[1 17 17 224]] | 30 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 213 | InceptionV4/InceptionV4/Mixed_6d/Branch_2/Conv2d_0d_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 1626.333 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 214 | InceptionV4/InceptionV4/Mixed_6d/Branch_2/Conv2d_0d_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 106.667 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 215 | InceptionV4/InceptionV4/Mixed_6d/Branch_2/Conv2d_0d_7x1/Relu | Relu | [[1 17 17 224]] | 29.667 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 216 | InceptionV4/InceptionV4/Mixed_6d/Branch_2/Conv2d_0e_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 256]] | 1725.333 | 295936 | 295936 | 0 | cpu | 0 | 0 | 0 | 0 |
| 217 | InceptionV4/InceptionV4/Mixed_6d/Branch_2/Conv2d_0e_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 256]] | 110.667 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 218 | InceptionV4/InceptionV4/Mixed_6d/concat | ConcatV2 | [[1 17 17 1024]] | 157.333 | 1183744 | 1183744 | 0 | cpu | 0 | 0 | 0 | 0 |
| 219 | InceptionV4/InceptionV4/Mixed_6d/Branch_0/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 1024]] | 113.667 | 1183744 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 220 | InceptionV4/InceptionV4/Mixed_6e/Branch_3/AvgPool_0a_3x3/AvgPool | AvgPool | [[1 17 17 1024]] | 1173 | 1183744 | 1183744 | 0 | cpu | 0 | 0 | 0 | 0 |
| 221 | InceptionV4/InceptionV4/Mixed_6e/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 3087.333 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 222 | InceptionV4/InceptionV4/Mixed_6e/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 192.333 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 223 | InceptionV4/InceptionV4/Mixed_6e/Branch_2/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 192]] | 27.333 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 224 | InceptionV4/InceptionV4/Mixed_6e/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 3386 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 225 | InceptionV4/InceptionV4/Mixed_6e/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 199.667 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 226 | InceptionV4/InceptionV4/Mixed_6e/Branch_1/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 192]] | 24.667 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 227 | InceptionV4/InceptionV4/Mixed_6e/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 128]] | 2560.333 | 147968 | 147968 | 0 | cpu | 0 | 0 | 0 | 0 |
| 228 | InceptionV4/InceptionV4/Mixed_6e/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 128]] | 354.667 | 147968 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 229 | InceptionV4/InceptionV4/Mixed_6e/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 384]] | 4993.667 | 443904 | 443904 | 0 | cpu | 0 | 0 | 0 | 0 |
| 230 | InceptionV4/InceptionV4/Mixed_6e/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 384]] | 294 | 443904 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 231 | InceptionV4/InceptionV4/Mixed_6e/Branch_2/Conv2d_0b_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 2724.667 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 232 | InceptionV4/InceptionV4/Mixed_6e/Branch_2/Conv2d_0b_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 140 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 233 | InceptionV4/InceptionV4/Mixed_6e/Branch_2/Conv2d_0b_7x1/Relu | Relu | [[1 17 17 192]] | 27 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 234 | InceptionV4/InceptionV4/Mixed_6e/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 2787.667 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 235 | InceptionV4/InceptionV4/Mixed_6e/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 197.333 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 236 | InceptionV4/InceptionV4/Mixed_6e/Branch_1/Conv2d_0b_1x7/Relu | Relu | [[1 17 17 224]] | 30.667 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 237 | InceptionV4/InceptionV4/Mixed_6e/Branch_2/Conv2d_0c_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 2412.667 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 238 | InceptionV4/InceptionV4/Mixed_6e/Branch_2/Conv2d_0c_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 146.667 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 239 | InceptionV4/InceptionV4/Mixed_6e/Branch_2/Conv2d_0c_1x7/Relu | Relu | [[1 17 17 224]] | 30 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 240 | InceptionV4/InceptionV4/Mixed_6e/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 256]] | 2920.333 | 295936 | 295936 | 0 | cpu | 0 | 0 | 0 | 0 |
| 241 | InceptionV4/InceptionV4/Mixed_6e/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 256]] | 132 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 242 | InceptionV4/InceptionV4/Mixed_6e/Branch_2/Conv2d_0d_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 1826 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 243 | InceptionV4/InceptionV4/Mixed_6e/Branch_2/Conv2d_0d_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 104 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 244 | InceptionV4/InceptionV4/Mixed_6e/Branch_2/Conv2d_0d_7x1/Relu | Relu | [[1 17 17 224]] | 32.667 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 245 | InceptionV4/InceptionV4/Mixed_6e/Branch_2/Conv2d_0e_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 256]] | 1745.333 | 295936 | 295936 | 0 | cpu | 0 | 0 | 0 | 0 |
| 246 | InceptionV4/InceptionV4/Mixed_6e/Branch_2/Conv2d_0e_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 256]] | 112 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 247 | InceptionV4/InceptionV4/Mixed_6e/concat | ConcatV2 | [[1 17 17 1024]] | 162.333 | 1183744 | 1183744 | 0 | cpu | 0 | 0 | 0 | 0 |
| 248 | InceptionV4/InceptionV4/Mixed_6e/Branch_0/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 1024]] | 115.333 | 1183744 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 249 | InceptionV4/InceptionV4/Mixed_6f/Branch_3/AvgPool_0a_3x3/AvgPool | AvgPool | [[1 17 17 1024]] | 1163 | 1183744 | 1183744 | 0 | cpu | 0 | 0 | 0 | 0 |
| 250 | InceptionV4/InceptionV4/Mixed_6f/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 4127 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 251 | InceptionV4/InceptionV4/Mixed_6f/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 141.667 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 252 | InceptionV4/InceptionV4/Mixed_6f/Branch_2/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 192]] | 26 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 253 | InceptionV4/InceptionV4/Mixed_6f/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 3576 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 254 | InceptionV4/InceptionV4/Mixed_6f/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 128]] | 2479.333 | 147968 | 147968 | 0 | cpu | 0 | 0 | 0 | 0 |
| 255 | InceptionV4/InceptionV4/Mixed_6f/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 156 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 256 | InceptionV4/InceptionV4/Mixed_6f/Branch_1/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 192]] | 27 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 257 | InceptionV4/InceptionV4/Mixed_6f/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 384]] | 4330 | 443904 | 443904 | 0 | cpu | 0 | 0 | 0 | 0 |
| 258 | InceptionV4/InceptionV4/Mixed_6f/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 128]] | 220.667 | 147968 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 259 | InceptionV4/InceptionV4/Mixed_6f/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 384]] | 299.667 | 443904 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 260 | InceptionV4/InceptionV4/Mixed_6f/Branch_2/Conv2d_0b_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 2245.667 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 261 | InceptionV4/InceptionV4/Mixed_6f/Branch_2/Conv2d_0b_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 129.333 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 262 | InceptionV4/InceptionV4/Mixed_6f/Branch_2/Conv2d_0b_7x1/Relu | Relu | [[1 17 17 192]] | 28 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 263 | InceptionV4/InceptionV4/Mixed_6f/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 2332 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 264 | InceptionV4/InceptionV4/Mixed_6f/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 131.667 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 265 | InceptionV4/InceptionV4/Mixed_6f/Branch_1/Conv2d_0b_1x7/Relu | Relu | [[1 17 17 224]] | 29.333 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 266 | InceptionV4/InceptionV4/Mixed_6f/Branch_2/Conv2d_0c_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 2437.667 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 267 | InceptionV4/InceptionV4/Mixed_6f/Branch_2/Conv2d_0c_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 117.667 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 268 | InceptionV4/InceptionV4/Mixed_6f/Branch_2/Conv2d_0c_1x7/Relu | Relu | [[1 17 17 224]] | 30 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 269 | InceptionV4/InceptionV4/Mixed_6f/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 256]] | 2875.333 | 295936 | 295936 | 0 | cpu | 0 | 0 | 0 | 0 |
| 270 | InceptionV4/InceptionV4/Mixed_6f/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 256]] | 190.667 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 271 | InceptionV4/InceptionV4/Mixed_6f/Branch_2/Conv2d_0d_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 1580.333 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 272 | InceptionV4/InceptionV4/Mixed_6f/Branch_2/Conv2d_0d_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 108.667 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 273 | InceptionV4/InceptionV4/Mixed_6f/Branch_2/Conv2d_0d_7x1/Relu | Relu | [[1 17 17 224]] | 31.333 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 274 | InceptionV4/InceptionV4/Mixed_6f/Branch_2/Conv2d_0e_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 256]] | 1724.333 | 295936 | 295936 | 0 | cpu | 0 | 0 | 0 | 0 |
| 275 | InceptionV4/InceptionV4/Mixed_6f/Branch_2/Conv2d_0e_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 256]] | 111 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 276 | InceptionV4/InceptionV4/Mixed_6f/concat | ConcatV2 | [[1 17 17 1024]] | 160.667 | 1183744 | 1183744 | 0 | cpu | 0 | 0 | 0 | 0 |
| 277 | InceptionV4/InceptionV4/Mixed_6f/Branch_0/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 1024]] | 117.667 | 1183744 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 278 | InceptionV4/InceptionV4/Mixed_6g/Branch_3/AvgPool_0a_3x3/AvgPool | AvgPool | [[1 17 17 1024]] | 1160.333 | 1183744 | 1183744 | 0 | cpu | 0 | 0 | 0 | 0 |
| 279 | InceptionV4/InceptionV4/Mixed_6g/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 3405.667 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 280 | InceptionV4/InceptionV4/Mixed_6g/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 3239.667 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 281 | InceptionV4/InceptionV4/Mixed_6g/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 252 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 282 | InceptionV4/InceptionV4/Mixed_6g/Branch_2/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 192]] | 26.333 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 283 | InceptionV4/InceptionV4/Mixed_6g/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 208 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 284 | InceptionV4/InceptionV4/Mixed_6g/Branch_1/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 192]] | 26.333 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 285 | InceptionV4/InceptionV4/Mixed_6g/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 128]] | 2457.333 | 147968 | 147968 | 0 | cpu | 0 | 0 | 0 | 0 |
| 286 | InceptionV4/InceptionV4/Mixed_6g/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 128]] | 192.667 | 147968 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 287 | InceptionV4/InceptionV4/Mixed_6g/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 384]] | 4816 | 443904 | 443904 | 0 | cpu | 0 | 0 | 0 | 0 |
| 288 | InceptionV4/InceptionV4/Mixed_6g/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 384]] | 351.667 | 443904 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 289 | InceptionV4/InceptionV4/Mixed_6g/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 2620 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 290 | InceptionV4/InceptionV4/Mixed_6g/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 111 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 291 | InceptionV4/InceptionV4/Mixed_6g/Branch_1/Conv2d_0b_1x7/Relu | Relu | [[1 17 17 224]] | 31 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 292 | InceptionV4/InceptionV4/Mixed_6g/Branch_2/Conv2d_0b_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 2554 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 293 | InceptionV4/InceptionV4/Mixed_6g/Branch_2/Conv2d_0b_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 138 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 294 | InceptionV4/InceptionV4/Mixed_6g/Branch_2/Conv2d_0b_7x1/Relu | Relu | [[1 17 17 192]] | 26.667 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 295 | InceptionV4/InceptionV4/Mixed_6g/Branch_2/Conv2d_0c_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 2314.667 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 296 | InceptionV4/InceptionV4/Mixed_6g/Branch_2/Conv2d_0c_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 156 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 297 | InceptionV4/InceptionV4/Mixed_6g/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 256]] | 3104 | 295936 | 295936 | 0 | cpu | 0 | 0 | 0 | 0 |
| 298 | InceptionV4/InceptionV4/Mixed_6g/Branch_2/Conv2d_0c_1x7/Relu | Relu | [[1 17 17 224]] | 28.667 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 299 | InceptionV4/InceptionV4/Mixed_6g/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 256]] | 181 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 300 | InceptionV4/InceptionV4/Mixed_6g/Branch_2/Conv2d_0d_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 1879 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 301 | InceptionV4/InceptionV4/Mixed_6g/Branch_2/Conv2d_0d_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 109.667 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 302 | InceptionV4/InceptionV4/Mixed_6g/Branch_2/Conv2d_0d_7x1/Relu | Relu | [[1 17 17 224]] | 30 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 303 | InceptionV4/InceptionV4/Mixed_6g/Branch_2/Conv2d_0e_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 256]] | 1747.667 | 295936 | 295936 | 0 | cpu | 0 | 0 | 0 | 0 |
| 304 | InceptionV4/InceptionV4/Mixed_6g/Branch_2/Conv2d_0e_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 256]] | 107.333 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 305 | InceptionV4/InceptionV4/Mixed_6g/concat | ConcatV2 | [[1 17 17 1024]] | 154 | 1183744 | 1183744 | 0 | cpu | 0 | 0 | 0 | 0 |
| 306 | InceptionV4/InceptionV4/Mixed_6g/Branch_0/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 1024]] | 114.667 | 1183744 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 307 | InceptionV4/InceptionV4/Mixed_6h/Branch_3/AvgPool_0a_3x3/AvgPool | AvgPool | [[1 17 17 1024]] | 1157 | 1183744 | 1183744 | 0 | cpu | 0 | 0 | 0 | 0 |
| 308 | InceptionV4/InceptionV4/Mixed_6h/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 3508.333 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 309 | InceptionV4/InceptionV4/Mixed_6h/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 223.667 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 310 | InceptionV4/InceptionV4/Mixed_6h/Branch_2/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 192]] | 27 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 311 | InceptionV4/InceptionV4/Mixed_6h/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 2914.667 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 312 | InceptionV4/InceptionV4/Mixed_6h/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 128]] | 2510.667 | 147968 | 147968 | 0 | cpu | 0 | 0 | 0 | 0 |
| 313 | InceptionV4/InceptionV4/Mixed_6h/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 187.667 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 314 | InceptionV4/InceptionV4/Mixed_6h/Branch_1/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 192]] | 27.667 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 315 | InceptionV4/InceptionV4/Mixed_6h/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 128]] | 428.333 | 147968 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 316 | InceptionV4/InceptionV4/Mixed_6h/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 384]] | 4588.333 | 443904 | 443904 | 0 | cpu | 0 | 0 | 0 | 0 |
| 317 | InceptionV4/InceptionV4/Mixed_6h/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 384]] | 303.667 | 443904 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 318 | InceptionV4/InceptionV4/Mixed_6h/Branch_2/Conv2d_0b_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 2418.333 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 319 | InceptionV4/InceptionV4/Mixed_6h/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 2878.333 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 320 | InceptionV4/InceptionV4/Mixed_6h/Branch_2/Conv2d_0b_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 174.667 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 321 | InceptionV4/InceptionV4/Mixed_6h/Branch_2/Conv2d_0b_7x1/Relu | Relu | [[1 17 17 192]] | 29 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 322 | InceptionV4/InceptionV4/Mixed_6h/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 112 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 323 | InceptionV4/InceptionV4/Mixed_6h/Branch_1/Conv2d_0b_1x7/Relu | Relu | [[1 17 17 224]] | 30.333 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 324 | InceptionV4/InceptionV4/Mixed_6h/Branch_2/Conv2d_0c_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 2658.333 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 325 | InceptionV4/InceptionV4/Mixed_6h/Branch_2/Conv2d_0c_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 102.667 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 326 | InceptionV4/InceptionV4/Mixed_6h/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 256]] | 2876 | 295936 | 295936 | 0 | cpu | 0 | 0 | 0 | 0 |
| 327 | InceptionV4/InceptionV4/Mixed_6h/Branch_2/Conv2d_0c_1x7/Relu | Relu | [[1 17 17 224]] | 33.333 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 328 | InceptionV4/InceptionV4/Mixed_6h/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 256]] | 127.333 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 329 | InceptionV4/InceptionV4/Mixed_6h/Branch_2/Conv2d_0d_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 224]] | 1563 | 258944 | 258944 | 0 | cpu | 0 | 0 | 0 | 0 |
| 330 | InceptionV4/InceptionV4/Mixed_6h/Branch_2/Conv2d_0d_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 224]] | 104.667 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 331 | InceptionV4/InceptionV4/Mixed_6h/Branch_2/Conv2d_0d_7x1/Relu | Relu | [[1 17 17 224]] | 30.333 | 258944 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 332 | InceptionV4/InceptionV4/Mixed_6h/Branch_2/Conv2d_0e_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 256]] | 1747.333 | 295936 | 295936 | 0 | cpu | 0 | 0 | 0 | 0 |
| 333 | InceptionV4/InceptionV4/Mixed_6h/Branch_2/Conv2d_0e_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 256]] | 113.667 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 334 | InceptionV4/InceptionV4/Mixed_6h/concat | ConcatV2 | [[1 17 17 1024]] | 161.667 | 1183744 | 1183744 | 0 | cpu | 0 | 0 | 0 | 0 |
| 335 | InceptionV4/InceptionV4/Mixed_6h/Branch_0/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 1024]] | 116.333 | 1183744 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 336 | InceptionV4/InceptionV4/Mixed_7a/Branch_2/MaxPool_1a_3x3/MaxPool | MaxPool | [[1 8 8 1024]] | 208.333 | 262144 | 262144 | 0 | cpu | 0 | 0 | 0 | 0 |
| 337 | InceptionV4/InceptionV4/Mixed_7a/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 192]] | 1736 | 221952 | 221952 | 0 | cpu | 0 | 0 | 0 | 0 |
| 338 | InceptionV4/InceptionV4/Mixed_7a/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 256]] | 2193.333 | 295936 | 295936 | 0 | cpu | 0 | 0 | 0 | 0 |
| 339 | InceptionV4/InceptionV4/Mixed_7a/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 192]] | 113.667 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 340 | InceptionV4/InceptionV4/Mixed_7a/Branch_0/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 192]] | 27 | 221952 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 341 | InceptionV4/InceptionV4/Mixed_7a/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 256]] | 124 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 342 | InceptionV4/InceptionV4/Mixed_7a/Branch_1/Conv2d_0a_1x1/Relu | Relu | [[1 17 17 256]] | 38.333 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 343 | InceptionV4/InceptionV4/Mixed_7a/Branch_0/Conv2d_1a_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 192]] | 856 | 49152 | 49152 | 0 | cpu | 0 | 0 | 0 | 0 |
| 344 | InceptionV4/InceptionV4/Mixed_7a/Branch_0/Conv2d_1a_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 192]] | 41 | 49152 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 345 | InceptionV4/InceptionV4/Mixed_7a/Branch_0/Conv2d_1a_3x3/Relu | Relu | [[1 8 8 192]] | 12.333 | 49152 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 346 | InceptionV4/InceptionV4/Mixed_7a/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 256]] | 2086.333 | 295936 | 295936 | 0 | cpu | 0 | 0 | 0 | 0 |
| 347 | InceptionV4/InceptionV4/Mixed_7a/Branch_1/Conv2d_0b_1x7/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 256]] | 113 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 348 | InceptionV4/InceptionV4/Mixed_7a/Branch_1/Conv2d_0b_1x7/Relu | Relu | [[1 17 17 256]] | 35.333 | 295936 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 349 | InceptionV4/InceptionV4/Mixed_7a/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm/mul | Conv2D | [[1 17 17 320]] | 2406.333 | 369920 | 369920 | 0 | cpu | 0 | 0 | 0 | 0 |
| 350 | InceptionV4/InceptionV4/Mixed_7a/Branch_1/Conv2d_0c_7x1/BatchNorm/batchnorm/add_1 | Add | [[1 17 17 320]] | 124.667 | 369920 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 351 | InceptionV4/InceptionV4/Mixed_7a/Branch_1/Conv2d_0c_7x1/Relu | Relu | [[1 17 17 320]] | 41.667 | 369920 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 352 | InceptionV4/InceptionV4/Mixed_7a/Branch_1/Conv2d_1a_3x3/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 320]] | 1426 | 81920 | 81920 | 0 | cpu | 0 | 0 | 0 | 0 |
| 353 | InceptionV4/InceptionV4/Mixed_7a/Branch_1/Conv2d_1a_3x3/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 320]] | 36.333 | 81920 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 354 | InceptionV4/InceptionV4/Mixed_7a/Branch_1/Conv2d_1a_3x3/Relu | Relu | [[1 8 8 320]] | 9.333 | 81920 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 355 | InceptionV4/InceptionV4/Mixed_7a/concat | ConcatV2 | [[1 8 8 1536]] | 111 | 393216 | 393216 | 0 | cpu | 0 | 0 | 0 | 0 |
| 356 | InceptionV4/InceptionV4/Mixed_7b/Branch_3/AvgPool_0a_3x3/AvgPool | AvgPool | [[1 8 8 1536]] | 399 | 393216 | 393216 | 0 | cpu | 0 | 0 | 0 | 0 |
| 357 | InceptionV4/InceptionV4/Mixed_7b/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 256]] | 1549.667 | 65536 | 65536 | 0 | cpu | 0 | 0 | 0 | 0 |
| 358 | InceptionV4/InceptionV4/Mixed_7b/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 256]] | 52.333 | 65536 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 359 | InceptionV4/InceptionV4/Mixed_7b/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 256]] | 1049 | 65536 | 65536 | 0 | cpu | 0 | 0 | 0 | 0 |
| 360 | InceptionV4/InceptionV4/Mixed_7b/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 256]] | 51.667 | 65536 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 361 | InceptionV4/InceptionV4/Mixed_7b/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 384]] | 2253.667 | 98304 | 98304 | 0 | cpu | 0 | 0 | 0 | 0 |
| 362 | InceptionV4/InceptionV4/Mixed_7b/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 384]] | 67 | 98304 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 363 | InceptionV4/InceptionV4/Mixed_7b/Branch_2/Conv2d_0a_1x1/Relu | Relu | [[1 8 8 384]] | 15.667 | 98304 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 364 | InceptionV4/InceptionV4/Mixed_7b/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 384]] | 2398 | 98304 | 98304 | 0 | cpu | 0 | 0 | 0 | 0 |
| 365 | InceptionV4/InceptionV4/Mixed_7b/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 384]] | 72.333 | 98304 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 366 | InceptionV4/InceptionV4/Mixed_7b/Branch_1/Conv2d_0a_1x1/Relu | Relu | [[1 8 8 384]] | 18.333 | 98304 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 367 | InceptionV4/InceptionV4/Mixed_7b/Branch_1/Conv2d_0b_1x3/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 256]] | 1152.667 | 65536 | 65536 | 0 | cpu | 0 | 0 | 0 | 0 |
| 368 | InceptionV4/InceptionV4/Mixed_7b/Branch_1/Conv2d_0c_3x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 256]] | 1120.667 | 65536 | 65536 | 0 | cpu | 0 | 0 | 0 | 0 |
| 369 | InceptionV4/InceptionV4/Mixed_7b/Branch_1/Conv2d_0b_1x3/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 256]] | 47.333 | 65536 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 370 | InceptionV4/InceptionV4/Mixed_7b/Branch_1/Conv2d_0c_3x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 256]] | 49 | 65536 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 371 | InceptionV4/InceptionV4/Mixed_7b/Branch_2/Conv2d_0b_3x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 448]] | 1332.667 | 114688 | 114688 | 0 | cpu | 0 | 0 | 0 | 0 |
| 372 | InceptionV4/InceptionV4/Mixed_7b/Branch_2/Conv2d_0b_3x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 448]] | 44.667 | 114688 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 373 | InceptionV4/InceptionV4/Mixed_7b/Branch_2/Conv2d_0b_3x1/Relu | Relu | [[1 8 8 448]] | 11.333 | 114688 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 374 | InceptionV4/InceptionV4/Mixed_7b/Branch_2/Conv2d_0c_1x3/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 512]] | 894 | 131072 | 131072 | 0 | cpu | 0 | 0 | 0 | 0 |
| 375 | InceptionV4/InceptionV4/Mixed_7b/Branch_2/Conv2d_0c_1x3/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 512]] | 47.333 | 131072 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 376 | InceptionV4/InceptionV4/Mixed_7b/Branch_2/Conv2d_0c_1x3/Relu | Relu | [[1 8 8 512]] | 12 | 131072 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 377 | InceptionV4/InceptionV4/Mixed_7b/Branch_2/Conv2d_0d_1x3/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 256]] | 992.667 | 65536 | 65536 | 0 | cpu | 0 | 0 | 0 | 0 |
| 378 | InceptionV4/InceptionV4/Mixed_7b/Branch_2/Conv2d_0d_1x3/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 256]] | 33.667 | 65536 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 379 | InceptionV4/InceptionV4/Mixed_7b/Branch_2/Conv2d_0e_3x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 256]] | 976.667 | 65536 | 65536 | 0 | cpu | 0 | 0 | 0 | 0 |
| 380 | InceptionV4/InceptionV4/Mixed_7b/Branch_2/Conv2d_0e_3x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 256]] | 35.667 | 65536 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 381 | InceptionV4/InceptionV4/Mixed_7b/concat | ConcatV2 | [[1 8 8 1536]] | 123 | 393216 | 393216 | 0 | cpu | 0 | 0 | 0 | 0 |
| 382 | InceptionV4/InceptionV4/Mixed_7b/Branch_0/Conv2d_0a_1x1/Relu | Relu | [[1 8 8 1536]] | 84 | 393216 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 383 | InceptionV4/InceptionV4/Mixed_7c/Branch_3/AvgPool_0a_3x3/AvgPool | AvgPool | [[1 8 8 1536]] | 400.333 | 393216 | 393216 | 0 | cpu | 0 | 0 | 0 | 0 |
| 384 | InceptionV4/InceptionV4/Mixed_7c/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 256]] | 1058.333 | 65536 | 65536 | 0 | cpu | 0 | 0 | 0 | 0 |
| 385 | InceptionV4/InceptionV4/Mixed_7c/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 256]] | 50.333 | 65536 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 386 | InceptionV4/InceptionV4/Mixed_7c/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 256]] | 1576.667 | 65536 | 65536 | 0 | cpu | 0 | 0 | 0 | 0 |
| 387 | InceptionV4/InceptionV4/Mixed_7c/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 256]] | 51 | 65536 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 388 | InceptionV4/InceptionV4/Mixed_7c/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 384]] | 2275.667 | 98304 | 98304 | 0 | cpu | 0 | 0 | 0 | 0 |
| 389 | InceptionV4/InceptionV4/Mixed_7c/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 384]] | 2240.667 | 98304 | 98304 | 0 | cpu | 0 | 0 | 0 | 0 |
| 390 | InceptionV4/InceptionV4/Mixed_7c/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 384]] | 50 | 98304 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 391 | InceptionV4/InceptionV4/Mixed_7c/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 384]] | 58 | 98304 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 392 | InceptionV4/InceptionV4/Mixed_7c/Branch_2/Conv2d_0a_1x1/Relu | Relu | [[1 8 8 384]] | 12.667 | 98304 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 393 | InceptionV4/InceptionV4/Mixed_7c/Branch_1/Conv2d_0a_1x1/Relu | Relu | [[1 8 8 384]] | 14 | 98304 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 394 | InceptionV4/InceptionV4/Mixed_7c/Branch_1/Conv2d_0c_3x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 256]] | 999 | 65536 | 65536 | 0 | cpu | 0 | 0 | 0 | 0 |
| 395 | InceptionV4/InceptionV4/Mixed_7c/Branch_1/Conv2d_0c_3x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 256]] | 52.333 | 65536 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 396 | InceptionV4/InceptionV4/Mixed_7c/Branch_1/Conv2d_0b_1x3/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 256]] | 1136 | 65536 | 65536 | 0 | cpu | 0 | 0 | 0 | 0 |
| 397 | InceptionV4/InceptionV4/Mixed_7c/Branch_1/Conv2d_0b_1x3/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 256]] | 52 | 65536 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 398 | InceptionV4/InceptionV4/Mixed_7c/Branch_2/Conv2d_0b_3x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 448]] | 1329.667 | 114688 | 114688 | 0 | cpu | 0 | 0 | 0 | 0 |
| 399 | InceptionV4/InceptionV4/Mixed_7c/Branch_2/Conv2d_0b_3x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 448]] | 42.667 | 114688 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 400 | InceptionV4/InceptionV4/Mixed_7c/Branch_2/Conv2d_0b_3x1/Relu | Relu | [[1 8 8 448]] | 10.667 | 114688 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 401 | InceptionV4/InceptionV4/Mixed_7c/Branch_2/Conv2d_0c_1x3/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 512]] | 892.333 | 131072 | 131072 | 0 | cpu | 0 | 0 | 0 | 0 |
| 402 | InceptionV4/InceptionV4/Mixed_7c/Branch_2/Conv2d_0c_1x3/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 512]] | 48.667 | 131072 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 403 | InceptionV4/InceptionV4/Mixed_7c/Branch_2/Conv2d_0c_1x3/Relu | Relu | [[1 8 8 512]] | 11.667 | 131072 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 404 | InceptionV4/InceptionV4/Mixed_7c/Branch_2/Conv2d_0e_3x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 256]] | 933.333 | 65536 | 65536 | 0 | cpu | 0 | 0 | 0 | 0 |
| 405 | InceptionV4/InceptionV4/Mixed_7c/Branch_2/Conv2d_0d_1x3/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 256]] | 943.333 | 65536 | 65536 | 0 | cpu | 0 | 0 | 0 | 0 |
| 406 | InceptionV4/InceptionV4/Mixed_7c/Branch_2/Conv2d_0e_3x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 256]] | 42 | 65536 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 407 | InceptionV4/InceptionV4/Mixed_7c/Branch_2/Conv2d_0d_1x3/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 256]] | 39.667 | 65536 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 408 | InceptionV4/InceptionV4/Mixed_7c/concat | ConcatV2 | [[1 8 8 1536]] | 119.667 | 393216 | 393216 | 0 | cpu | 0 | 0 | 0 | 0 |
| 409 | InceptionV4/InceptionV4/Mixed_7c/Branch_0/Conv2d_0a_1x1/Relu | Relu | [[1 8 8 1536]] | 81.667 | 393216 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 410 | InceptionV4/InceptionV4/Mixed_7d/Branch_3/AvgPool_0a_3x3/AvgPool | AvgPool | [[1 8 8 1536]] | 393.333 | 393216 | 393216 | 0 | cpu | 0 | 0 | 0 | 0 |
| 411 | InceptionV4/InceptionV4/Mixed_7d/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 256]] | 1303.667 | 65536 | 65536 | 0 | cpu | 0 | 0 | 0 | 0 |
| 412 | InceptionV4/InceptionV4/Mixed_7d/Branch_3/Conv2d_0b_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 256]] | 49 | 65536 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 413 | InceptionV4/InceptionV4/Mixed_7d/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 256]] | 1523.667 | 65536 | 65536 | 0 | cpu | 0 | 0 | 0 | 0 |
| 414 | InceptionV4/InceptionV4/Mixed_7d/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 384]] | 2195.333 | 98304 | 98304 | 0 | cpu | 0 | 0 | 0 | 0 |
| 415 | InceptionV4/InceptionV4/Mixed_7d/Branch_0/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 256]] | 54.333 | 65536 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 416 | InceptionV4/InceptionV4/Mixed_7d/Branch_2/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 384]] | 57.333 | 98304 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 417 | InceptionV4/InceptionV4/Mixed_7d/Branch_2/Conv2d_0a_1x1/Relu | Relu | [[1 8 8 384]] | 11.667 | 98304 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 418 | InceptionV4/InceptionV4/Mixed_7d/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 384]] | 2331 | 98304 | 98304 | 0 | cpu | 0 | 0 | 0 | 0 |
| 419 | InceptionV4/InceptionV4/Mixed_7d/Branch_1/Conv2d_0a_1x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 384]] | 59 | 98304 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 420 | InceptionV4/InceptionV4/Mixed_7d/Branch_1/Conv2d_0a_1x1/Relu | Relu | [[1 8 8 384]] | 16.667 | 98304 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 421 | InceptionV4/InceptionV4/Mixed_7d/Branch_1/Conv2d_0b_1x3/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 256]] | 1059.667 | 65536 | 65536 | 0 | cpu | 0 | 0 | 0 | 0 |
| 422 | InceptionV4/InceptionV4/Mixed_7d/Branch_1/Conv2d_0b_1x3/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 256]] | 52.333 | 65536 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 423 | InceptionV4/InceptionV4/Mixed_7d/Branch_1/Conv2d_0c_3x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 256]] | 1029.667 | 65536 | 65536 | 0 | cpu | 0 | 0 | 0 | 0 |
| 424 | InceptionV4/InceptionV4/Mixed_7d/Branch_1/Conv2d_0c_3x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 256]] | 50.333 | 65536 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 425 | InceptionV4/InceptionV4/Mixed_7d/Branch_2/Conv2d_0b_3x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 448]] | 1334.667 | 114688 | 114688 | 0 | cpu | 0 | 0 | 0 | 0 |
| 426 | InceptionV4/InceptionV4/Mixed_7d/Branch_2/Conv2d_0b_3x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 448]] | 54.333 | 114688 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 427 | InceptionV4/InceptionV4/Mixed_7d/Branch_2/Conv2d_0b_3x1/Relu | Relu | [[1 8 8 448]] | 13.333 | 114688 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 428 | InceptionV4/InceptionV4/Mixed_7d/Branch_2/Conv2d_0c_1x3/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 512]] | 867.667 | 131072 | 131072 | 0 | cpu | 0 | 0 | 0 | 0 |
| 429 | InceptionV4/InceptionV4/Mixed_7d/Branch_2/Conv2d_0c_1x3/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 512]] | 49.667 | 131072 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 430 | InceptionV4/InceptionV4/Mixed_7d/Branch_2/Conv2d_0c_1x3/Relu | Relu | [[1 8 8 512]] | 12 | 131072 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 431 | InceptionV4/InceptionV4/Mixed_7d/Branch_2/Conv2d_0e_3x1/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 256]] | 933.667 | 65536 | 65536 | 0 | cpu | 0 | 0 | 0 | 0 |
| 432 | InceptionV4/InceptionV4/Mixed_7d/Branch_2/Conv2d_0e_3x1/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 256]] | 36.667 | 65536 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 433 | InceptionV4/InceptionV4/Mixed_7d/Branch_2/Conv2d_0d_1x3/BatchNorm/batchnorm/mul | Conv2D | [[1 8 8 256]] | 948.667 | 65536 | 65536 | 0 | cpu | 0 | 0 | 0 | 0 |
| 434 | InceptionV4/InceptionV4/Mixed_7d/Branch_2/Conv2d_0d_1x3/BatchNorm/batchnorm/add_1 | Add | [[1 8 8 256]] | 35.333 | 65536 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 435 | InceptionV4/InceptionV4/Mixed_7d/concat | ConcatV2 | [[1 8 8 1536]] | 120.667 | 393216 | 393216 | 0 | cpu | 0 | 0 | 0 | 0 |
| 436 | InceptionV4/InceptionV4/Mixed_7d/Branch_0/Conv2d_0a_1x1/Relu | Relu | [[1 8 8 1536]] | 81.667 | 393216 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 437 | InceptionV4/Logits/AvgPool_1a/AvgPool | AvgPool | [[1 1 1 1536]] | 45.667 | 6144 | 6144 | 0 | cpu | 0 | 0 | 0 | 0 |
| 438 | InceptionV4/Logits/PreLogitsFlatten/Shape | Shape | [[4]] | 10.667 | 16 | 16 | 0 | cpu | 0 | 0 | 0 | 0 |
| 439 | InceptionV4/Logits/PreLogitsFlatten/Slice | Slice | [[1]] | 12 | 4 | 4 | 0 | cpu | 0 | 0 | 0 | 0 |
| 440 | InceptionV4/Logits/PreLogitsFlatten/Slice_1 | Slice | [[3]] | 16 | 12 | 12 | 0 | cpu | 0 | 0 | 0 | 0 |
| 441 | InceptionV4/Logits/PreLogitsFlatten/Prod | Prod | [[]] | 17.333 | 4 | 4 | 0 | cpu | 0 | 0 | 0 | 0 |
| 442 | InceptionV4/Logits/PreLogitsFlatten/ExpandDims | ExpandDims | [[1]] | 7.667 | 4 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 443 | InceptionV4/Logits/PreLogitsFlatten/concat | ConcatV2 | [[2]] | 14 | 8 | 8 | 0 | cpu | 0 | 0 | 0 | 0 |
| 444 | InceptionV4/Logits/PreLogitsFlatten/Reshape | Reshape | [[1 1536]] | 7 | 6144 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 445 | InceptionV4/Logits/Logits/MatMul | MatMul | [[1 1001]] | 592 | 4004 | 4004 | 0 | cpu | 0 | 0 | 0 | 0 |
| 446 | InceptionV4/Logits/Logits/BiasAdd | BiasAdd | [[1 1001]] | 11 | 4004 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
| 447 | InceptionV4/Logits/Predictions | Softmax | [[1 1001]] | 40.333 | 4004 | 0 | 0 | cpu | 0 | 0 | 0 | 0 |
Showing 1 to 446 of 446 entries